14th Asian Test Symposium, ATS'05
------------------------------------------------------------------------
2005 IEEEAsian Test Symposium
December 18-21, 2005
Hyatt Regency Hotel, Salt Lake City, Kolkata, India
Asian Test Symposium 2005 (ATSf05) is the fourteenth in a series of
annual international symposia on VLSI testing. This symposium aims to
provide an open forum for researchers, developers, designers, and industrial
practitioners worldwide to exchange ideas on test technology. This year the
theme is embedded test technology, and will cover all aspects of design for
testability, test integration, diagnosis, repair, and yield enhancement of
complex chips with embedded digital/analog/memory components.
SCOPE:
Original papers on VLSI testing are solicited. Topics of interest include, but
are not limited to, the following categories:
1. Test generation & fault simulation
2. Design for testability
3. Fault diagnosis
4. Analog & mixed-signal testing
5. Memory testing
6. Wafer-level testing
7. System-on-chip testing
8. MEMS testing
9. Software testing
10. CPU testing
11. Failure analysis & fault modeling
12. Built-in self-test
13. Fault tolerance & error correction
14. Functional testing
15. IDDQ testing
16. Test economics
17. Boundary scan
18. Industrial practice and experiences
19. Automatic test equipment
20. Yield enhancement
21. On-line testing
22. Verification & simulation
SUBMISSION:
All submission should be made electronically in PDF format at http://www.iitkgp.ac.in/ats05/.
A submission should contain a complete manuscript within a limit 6 pages in 10-point single-
spaced double-column format, an abstract of 50-200 words, and a separate cover page,
clearly indicating (1) the title of the paper, (2) the affiliation of each author, (3) the contact
author (including the postal and e-mail addresses), and (4) the categories of the topic.
Once a submission is accepted, the author(s) must prepare the final camera-ready manuscript
in time for being included in the proceedings, and present the paper at the symposium. In case
of any difficulty in submission, authors may contact ats05@iitkgp.ac.in.
IMPORTANT DATES:
Paper submission deadline:
June 3, 2005
Notification of acceptance:
August 1, 2005
Camera-ready paper due:
September 1, 2005
ORGANIZING COMMITTEE
GENERAL CHAIR
Indranil Sengupta
Indian Institute of Technology, Kharagpur, India
Email: isg(at)iitkgp.ac.in
PROGRAM CO-CHAIRS
Krishnendu Chakrabarty
Duke University, USA
E-mail: krish(at)ee.duke.edu
Dipanwita Roy Chowdhury
Indian Institute of Technology, Kharagpur, India
E-mail: drc(at)cse.iitkgp.ernet.in
ORGANIZING CO-CHAIRS
Debesh Kumar Das
Jadavpur University, India
E-mail: debeshd(at)hotmail.com
Probal Sengupta
Alumnus Software, Kolkata, India
E-mail: probal(at)alumnux.com
FINANCE CHAIR
Biplab Kumar Sikdar
Bengal Engg & Science University, India
E-mail: biplab(at)cs.becs.ac.in
LOCAL ARRANGEMENTS CHAIR
Niloy Ganguly
IISWBM, Kolkata, India
Email: n_ganguly(at)hotmail.com
TUTORIAL CHAIR
Kaushik Roy
Purdue University, USA
E-mail: kaushik(at)ecn.purdue.edu
INDUSTRIAL SESSIONS CHAIR
Srivaths Ravi
NEC Labs, USA
E-mail: sravi(at)nec-labs.com
REGISTRATION CHAIR
Hafizur Rahaman
Bengal Engg & Science University, India
E-mail: rahaman_h(at)hotmail.com
PUBLICATIONS CHAIR
Susanta Sen
University of Calcutta, India
E-mail: susanta(at)mail.inraphel.ernet.in
PUBLICITY CHAIR
Susanta Chakraborty
Kalyani University, India
E-mail: susanta_chak(at)hotmail.com
INDUSTRIAL LIAISON CHAIRS
Susanta Misra
Motorola India Limited, India
E-mail: susanta.misra(at)motorola.com
Biswadip Mitra
Texas Instruments, India
E-mail: bmitra(at)ti.com
NORTH AMERICAN LIAISON
Sudipta Bhawmik
Agere Systems, USA
E-mail: bhawmik(at)agere.com
EUROPEAN LIAISON
Dhiraj K Pradhan
University of Bristol, UK
E-mail: pradhan(at)cs.bris.ac.uk
PROGRAM COMMITTEE
1. Seiji Kajihara, Kyushu Institute of Technology, Japan
2. Tomoo Inoue, Hiroshima City University, Japan
3. Hiromi Hiraishi, Kyoto Sangio University, Japan
4. Michiko Inoue, NAIST, Japan
5. Kiyoshi Furuya, Chuo University, Japan
6. Masaki Hashizume, University of Tokushima, Japan
7. Kazumi Hatayama, Renesas Technology Corpn, Japan
8. Hiroshi Takahashi, Ehime University, Japan
9. Dong Xiang, Tsinghua University, China
10. Y.-H. Min, Chinese Academy of Sciences, China
11. Xiaowei Li, Chinese Academy of Sciences, China
12. Shiyi Xu, Shanghai University, China
13. Kuen-Jong Lee, National Cheng-Kung Univ, Taiwan
14. Shi-Yu Huang, National Tsing Hua University, Taiwan
15. Cheng-Wen Wu, National Tsing Hua University, Taiwan
16. Serge Demidenko, Monash University, Malaysia
17. Zainalabedin Navabi, University of Tehran, Iran
18. Rubin Parekhji, Texas Instruments, India
19. V. Kamakoti, IIT Madras, India
20. Santanu Chattopadhyay, IIT Kharagpur, India
21. Supratik Chakraborty, IIT Bombay, India
22. Anshul Kumar, IIT Delhi, India
23. Shashank Mehta, IIT Kanpur, India
24. Kolin Paul, IIT Delhi, India
25. Siddhartha Mukhopadhyay, IIT Kharagpur, India
26. Dipankar Sarkar, IIT Kharagpur, India
27. Ajit Pal, IIT Kharagpur, India
28. Sujit T. Zachariah, Intel Corporation, India
29. Samir Roy, Kalyani Government Engg College, India
30. Jayanta Lahiri, Alliance Semiconductor, India
31. Abhik Mukherjee, Bengal Engineering and Science University, India
32. Nicola Nicolici, McMaster University, Canada
33. Erik Jan Marinissen, Philips, Netherlands
34. Michel Renovell, LIRMM, France
35. Patrick Girard, LIRRM, France
36. Sybille Hellebrand, Innsbruck University, Austria
37. Hans-Joachim Wunderlich, University of Stuttgart, Germany
38. Zebo Peng, Linkpoing University, Sweden
39. Sule Ozev, Duke University, USA
40. Mani Soma, University of Washington, USA
41. Shawn Blanton, Carnegie-Melon University, USA
42. K.-T. Cheng, Univ. of California at Santa Barbara, USA
43. Li-C. Wang, Univ of California at Santa Barbara, USA
44. Sudhakar Reddy, University of Iowa, USA
45. Vishani D. Agrawal, Auburn University, USA
46. Michael Hsiao, Virginia Tech, USA
47. Niraj K Jha, Princeton University, USA
48. Indradeep Ghosh, Fujitsu Labs, USA
-------------------------------------------
December 18, 2005
8:30 | 11:00
Plenary Session
Inauguration
Chair: B.B. Bhattacharyya, Indian Statistical Institute, Kolkata, India
Plenary Talk: T.W. Williams, Synopsys, USA
Invited (Plenary) Talk: John P. Hayes, University of Michigan, USA
11:00 | 11:30
Tea/Coffee Break
11:30 | 13:00
Session A1
Analog and RF Testing: I
Session B1
Verification, On-line and Software Testing
Industry Session C1
SoC Test Practices
13:00 | 14:00
Lunch Break
14:00 | 15:30
Session A2
Analog and RF Testing: II
Session B2
Self-Checking, On-line and Software Testing
Industry Session C2
Defect-Based Testing
15:30 | 16:00
Tea/Coffee Break
16:00 | 17:30
Session A3
Interconnect Testing
Session B3
BIST
Embedded Test Technologies Panel
Moderator: Rob Roy (Zenasis)
Srimat Chakradhar (NEC)
Rubin Parekhji (TI)
Praveen Parvathala (Intel)
Mohan Yegnashankaran (NSC)
18:00 | 21:30
Banquet (Venue: Hyatt Regency Hotel)
Chair: Partha Pratim Das, Interra Systems, India
Banquet Talk: Janusz Rajski, Mentor Graphics Corpn., USA
Cultural Function
Dinner
December 19, 2005
8:30 | 9:30
Invited Talk
Chair: Vishani D. Agrawal, Auburn University, USA
Speaker: Sreejit Chakravarty, Intel Corpn., USA
9:30 | 11:00
Session A4
SoC Testing
Session B4
Yield Enhancement
Industry Session C4
Advances in Test Generation and Verification
11:00 | 11:30
Tea/Coffee Break
11:30 | 13:00
Session A5
Delay and Defect-Based Testing
Session B5
Low Power Testing
Industry Session C5
Test Data Compression and System Level Testing
13:00 | 14:00
Lunch Break
14:00 | 15:30
Session A6
Diagnosis, Delay, and Defect-Based Testing
Session B6
Test Generation and Fault Simulation
Industry Session C6
Mixed Signal Testing
15:30 | 16:00
Tea/Coffee Break
16:00 | 17:30
Session A7
Design for Testability: I
Session B7
Test Compression and Compaction
Industry Session C7
Delay Testing and Burn-in Test Methodologies
17:30 | 19:00
Cadence Banquet Talk (Venue: Hyatt Regency Hotel)
Chair: C.P. Ravikumar, Texas Instruments, Bangalore, India
Banquet Talk: Sanjiv Taneja, Cadence, USA
19:30 | 21:30
Cadence Banquet Dinner (Venue: Swabhumi)
December 20, 2005
8:00 | 9:30
Session A8
Design for Testability: II
Session B8
Test Compression, Test Compaction, and Defect-Based testing
9:30 | 11:00
Session A9
Design for Testability: III
Session B9
Fault Modeling, Processor Testing, and Memory Testing
11:00 | 11:30
Tea/Coffee Break
11:30 | 13:00
Panel Discussion
Beyond Circa 2005: The Road Ahead in R&D for Testing
Moderator: Debashis Bhattacharya, Zenasis Technologies, USA
Hideo Fujiwara, Nara Institute of Science & Technology, Japan
Nilanjan Mukherjee, Mentor Graphics Corpn., USA
Vishwani D. Agrawal, Auburn University, USA
T.M. Mak, Intel Corpn., USA
Salvador Mir, TIMA Laboratory, France
Nirankar Saxena, Joint Director, FICCI, India
13:00 | 13:15
Closing Session
13:15 | 14:15
Lunch Break
14:30 onwards
Sight Seeing Tour
December 21, 2005
9:00 | 12:00
Tutorial A1
Design for Manufacturability
Juan-Antonio Carballo
Tutorial B1
Statistical Methods for VLSI Test and Burn-in Optimization
Adit Singh
12:00 | 13:30
Lunch Break
13:30 | 16:30
Tutorial A2
Design for Manufacturability
Juan-Antonio Carballo
Tutorial B2
Statistical Methods for VLSI Test and Burn-in Optimization
Adit Singh
TECHNICAL PAPERS (REGULAR and SHORT)
Session A1: Analog and RF Testing: I
CHAIR: Michell Renovell, LIRRM, France
[Regular] Robust built-in test of RF ICs using envelope detectors
D. Han and A. Chatterjee (Georgia Institute of Technology, USA)
[Regular] Delay defect characterization using low voltage test
H. Yan (Synopsys Inc., USA), A.D. Singh, and G. Xu (Auburn University, USA)
[Short] Alternate test methodology for high speed A/DC testing on low cost tester
S. Goyal and A. Chatterjee (Georgia Institute of Technology, USA)
[Short] IDDQ testing method using a scan pattern for production testing
J. Hirase, Y.I. Goi, and Y. Tanak (Matsushita Electric Industrial Co. Ltd., Japan)
[Short] A new, flexible and very accurate crosstalk fault model to analyze the
effects of coupling noise between the interconnects on signal integrity losses
in deep submicron chips
A.K. Palit, L. Wu, K.K. Duganapalli, W. Anheier (University of Bremen, Germany),
and J. Schloeffel (Philips Semiconductors GmbH, Germany)
Session B1: Verification, On-line and Software Testing
CHAIR: Partha Pratim Chakrabarti, Indian Institute of Technology, Kharagpur, India
[Regular] An efficient system-level to RTL verification framework for computation-intensive applications
N.D. Liveris, H. Zhou (Northwestern University, USA), and P. Banerjee (University of Illinois, USA)
[Regular] Block-based schema-driven assertion generation for functional verification
A. Hekmatpour (IBM North Carolina, USA) and A. Salehi (North Carolina State University, USA)
[Regular] A framework for automatic assembly program generator (A2PG) for functional
verification and testing of processor cores
K.U. Bhaskar, M. Prasanth, V. Kamakoti (Indian Institute of Technology, Madras, India),
and M. Kailasnath (Intel Corporation Santa Clara, USA)
[Short] The automatic generation of basis set of path in path testing
Z. Guangmei, C. Rui, L. Xiaowei (Chinese Academy of Sciences, Beijing, China), and H. Congying
(Shan Dong University of Science and Technology, China)
Session A2: Analog and RF Testing: II
CHAIR: Sidhhartha Mukhopadhyay, Indian Institute of Technology, Kharagpur, India
[Regular] Optimal schemes for ADC BIST based on histogram
W. Yong-Sheng, W. Jin-Xiang, L. Feng-Chang, and Y. Yi-Zheng (Harbin Institute of Technology, China)
[Regular] A 5 Gbps wafer-level tester
A.M. Majid, D.C. Keezer, and J.V. Karia (Georgia Institute of Technology, USA)
[Regular] Low-cost production test of wireless receivers for bit error rate
A. Halder and A. Chatterjee (Georgia Institute of Technology, USA)
[Short] Design of a operational amplifier amenable to extreme voltage stress
S. Quan (Michigan State University, USA) and C-L. Wey (National Central University, Chung-Li, Taiwan)
Session B2: Self-Checking, On-line and Software Testing
CHAIR: Satoshi Ohtake, Nara Institute of Science and Technology, Japan
[Regular] New self-checking output-duplicated Booth multiplier with high fault coverage for soft errors
D. Marienfeld, E. S. Sogomonyan, V. Ocheretnij, and M. Goessel (University of Potsdam, Germany)
[Regular] A state machine for detecting C/C++ memory faults
G. Huang, G. Zhang, X. Li, and Y. Gong (Institute of Computing Technology, CAS Beijing, China)
[Regular] On-line testing of digital circuits for n-detect and bridging fault models
P. Srikanth, S. Biswas, S. Mukhopadhyay, A. Patra, and D. Sarkar (Indian Institute of Technology, Kharagpur, India)
[Short] Boundary value testing based on UML models
P. Samuel and R. Mall (Indian Institute of Technology, Kharagpur, India)
Session A3: Interconnect Testing
CHAIR: Sandip Kundu, University of Massachusetts, USA
[Regular] Random jitter testing using low tap-count delay lines
J-L. Huang (National Taiwan University, Taiwan)
[Regular] Crosstalk fault detection for interconnection lines based on path delay inertia principle
M-S. Wu, C-L. Lee (National Chiao Tung University, Taiwan), Y-J. Chang, and W-C. Wu
(Industrical Technology Research Institute, Taiwan)
[Regular] Upper bound on the amplitude of crosstalk pulse and methodology to compute
bounds on crosstalk effects in arbitrary interconnects
W. Sirisaengtaksin and S.K. Gupta (University of Southern California, USA)
[Short] Non-robust test generation for crosstalk-induced delay faults
P-F. Shen, H-W. Li, Y-J. Xu, and X-W. Li (Chinese Academy of Sciences, Beijing, China)
Session B3: BIST
CHAIR: Christian Landrault, LIRRM, France
[Regular] Using weighted random test control signals to improve the effectiveness of scan-based BIST
D. Xiang, M. Chen (Tsinghua University, Beijing, China), and H. Fujiwara
(Nara Institute of Science and Technology, Japan)
[Regular] Circuit independent weighted pseudo-random BIST pattern generator
C. Yu, S.M. Reddy (University of Iowa, USA), and I. Pomeranz (Purdue University, USA)
[Regular] Low transition LFSR for BIST-based applications
M. Tehranipoor (University of Maryland Baltimore, USA), M. Nourani (University of Texas, Dallas, USA),
and N. Ahmed (Texas Instruments, USA)
[Short] A BIST scheme based on selecting state generation of folding counters
H. Liang, M. Yi, X. Fang, and C. Jiang (Hefei University of Technology, China)
Session A4: SoC Testing
CHAIR: Santanu Chattopadhyay, Indian Institute of Technology, Kharagpur, India
[Regular] Power-constrained area and time co-optimization for SoCs based on consecutive testability
T. Yoneda (Nara Institute of Science and Technology, Japan), H. Takakuwa (RICOH, Japan), and
H. Fujiwara (Nara Institute of Science and Technology, Japan)
[Regular] Low cost delay testing of nanometer SoCs using on-chip clocking and test compression
H. Nakamura, A. Shirokane, Y. Nishizaki (Kawasaki Microelectronics, Japan), A. Uzzaman, V. Chickermane,
B. Keller (Cadence Design Systems Inc., USA), T. Ube, and Y. Terauchi (Innotech Corporation, Yokohama, Japan)
[Regular] SOC test scheduling with test set sharing and broadcasting
A. Larsson, E. Larsson, P. Eles, and Z. Peng (Embedded Systems Laboratory, Linkopings Universitet, Sweden)
Session B4: Yield Enhancement
CHAIR: Xiaoqing Wen, Kyushu Institute of Technology, Japan
[Regular] A statistical approach to area-constrained yield enhancement for pipelined circuits
under parameter variations
A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy (Purdue University, USA)
[Regular] Leakage current based stabilization scheme for robust sense-amplifier design for
yield enhancement in nano-scale SRAM
S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy (Purdue University, USA)
[Regular] Flash memory die sort by a sample classification method
Y-C. Dawn, J-C. Yeh, C-W. Wu (National Tsing Hua University, Taiwan), C-C. Wang, Y-C. Lin,
and C-H. Chen (Windbond Electronics Corporation, Taiwan)
[Short] Chip identification using the characteristic dispersion of transistor
J. Hirase and T. Furukawa (Matsushita Electric Industrial Co. Ltd., Japan)
Session A5: Delay and Defect-Based Testing
CHAIR: Masaki Hashizume, University of Tokushima, Japan
[Regular] Untestable multi-cycle path delay faults in industrial designs
M. Syal (Virginia Tech, USA), S. Natarajan, S. Chakravarty (Intel Corporation, Santa Clara, USA),
and M.S. Hsiao (Virginia Tech, USA)
[Regular] Improved delay fault coverage using subsets of flip-flops to launch transitions
N. Devtaprasanna (University of Iowa, USA), A. Gunda, P. Krishnamurthy (LSI Logic Corporation, USA),
and S.M. Reddy (University of Iowa, USA)
[Regular] Selection of paths for delay testing
I-De Huang and S.K. Gupta (University of Southern California, USA)
[Short] On improving defect coverage of stuck-at fault tests
K. Miyase (Japan Science and Technology Agency, Japan), K. Terashima, S. Kajihara, X. Wen
(Kyushu Institute of Technology, Japan), and S.M. Reddy (University of Iowa, USA)
Session B5: Low Power Testing
CHAIR: Rubin Parekhji, Texas Instruments, Bangalore, India
[Regular] A scan matrix design for low power scan-based test
S. P. Lin, C. L. Lee (National Chiao Tung University, Taiwan), and J. E. Chen (National Central University, Taiwan)
[Regular] A new low power test pattern generator using a transition monitoring window based on BIST architecture
Y. Kim, M-H. Yang, Y. Lee, and S. Kang (Yonsei University, Seoul, Korea)
[Regular] ISC: Reconfigurable scan-cell architecture for low power testing
H. Esmaeilzadeh, S. Shamshiri, P. Saeedi, and Z. Navabi (University of Tehran, Iran)
[Short] Partial gating optimization for power reduction during test application
M. ElShoukry (University of Maryland, USA), C.P. Ravikumar (Texas Instruments, India), and
M. Tehranipoor (University of Maryland, USA)
Session A6: Diagnosis, Delay, and Defect-Based Testing
CHAIR: T.J. Chakraborty, Lucent Technologies, USA
[Regular] Bridge defect diagnosis with physical information
W. Zou (University of Iowa, USA), W-T. Cheng (Mentor Graphics Corporation, Wilsonville, USA),
and S.M. Reddy (University of Iowa, USA)
[Regular] Design for testability based on single-port-change delay testing for data paths
Y. Yoshikawa, S. Ohtake, M. Inoue, and H. Fujiwara (Nara Institute of Science and Technology, Japan)
[Regular] A class of linear space compactors for enhanced diagnostic
T. Clouqueur (Nara Institute of Science and Technology, Japan), K.K. Saluja (University of Wisconsin-Madison, USA),
and H. Fujiwara (Nara Institute of Science and Technology, Japan)
[Short] On detection of resistive bridging defects by low-temperature and low-voltage testing
S. Kundu (University of Massachusetts, USA), P. Engelke, I. Polian, and B. Becker (Albert Ludwigs University, Germany)
Session B6: Test Generation and Fault Simulation
CHAIR: Raimund Ubar, Tallinn Technical University, Estonia
[Regular] State-reuse test generation for progressive random access scan: solution to test power,
application time and data size
D.H. Baik and K.K. Saluja (University of Wisconsin-Madison, USA)
[Regular] Enhancing fault simulation performance by dynamic fault clustering
S. Mirkhani and Z. Navabi (University of Tehran, Iran)
[Short] Cost optimal design of nonlinear CA based PRPG for test applications
S. Das, H. Rahaman, and B.K. Sikdar (Bengal Engineering and Science University, India)
[Short] An effective design for hierarchical test generation based on strong testability
H. Ichihara, N. Okamoto, T. Inoue (Hiroshima City University, Japan), T. Hosokawa (Nihon University, Japan),
and H. Fujiwara (Nara Institute of Science and Technology, Japan)
[Short] Concurrent test generation
V.D. Agrawal and A.S. Doshi (Auburn University, USA)
Session A7: Design for Testability: I
CHAIR: Kolin Paul, Indian Institute of Technology, Delhi, India
[Regular] Novel bi-partitioned scan architecture to improve transition fault coverage
V.R. Devanathan (Texas Instruments, Bangalore, India)
[Regular] A DFT method for RTL data paths based on partially strong testability to guarantee complete fault efficiency
H. Iwata, T. Yoneda, S. Ohtake, and H. Fujiwara (Nara Institute of Science and Technology, Japan)
[Regular] Achieving high test quality with reduced pin count testing
J. Jahangiri, N. Mukherjee, W-T. Cheng, S. Mahadevan, and R. Press (Mentor Graphics Corporations, USA)
[Short] Design for cost effective scan testing by reconfiguring scan flip-flops
D. Xiang, K-W. Li (Tsinghua University, China), and H. Fujiwara (Nara Institute of Science and Technology, Japan)
Session B7: Test Compression and Compaction
CHAIR: Ilia Polian, Albert Ludwigs University of Freiburg, Germany
[Regular] Adaptive encoding scheme for test volume/time reduction in SoC scan testing
S.P. Lin, C.L. Lee, and J.E. Chen (National Central University, Taiwan)
[Regular] Choosing the right mix of at-speed structural test patterns: comparisons in pattern volume
reduction and fault detection efficiency
S. Goel and R.A. Parekhji (Texas Instruments, Bangalore, India)
[Regular] Efficient test compaction for pseudo-random testing
S. Zhang, S.C. Seth (University of Nebraska Lincoln, USA), and B.B. Bhattacharya
(Indian Statistical Institute, Kolkata, India)
[Short] Test data compression with partial LFSR-reseeding
Y-H. Fu and S-J. Wang (National Chung Hsing University, Taiwan)
Session A8: Design for Testability: II
CHAIR: Dong Xiang, Tsinghua University, China
[Regular] CryptoScan: A secured scan chain architecture
D.Mukhopadhyay, S.Banerjee, D.Roy Chowdhury (Indian Institute of Technology, Kharagpur, India),
and B.B. Bhattacharya (Indian Statistical Institute, Kolkata, India)
[Regular] Pseudo-parity testing and testable design
Shiyi Xu (Shanghai University, China)
[Regular] Finite state machine synthesis for at-speed oscillation testability
K.S-M. Li, C.L. Lee (National Chiao Tung University, Taiwan), T. Jiang (Via Technologies, Inc., C. Su,
and J.E. Chen (National Central University, Taiwan)
[Short] A test cost reduction method by test response and test vector overlapping for full-scan test architecture
T. Shinogi, H. Yamada, T. Hayashi (Mie University, Japan), T. Yoshikawa (Nagoya University, Japan),
and S. Tsuruoka (Mie University, Japan)
Session B8: Test Compression, Test Compaction, and Defect-Based Testing
CHAIR: Kewal K. Saluja, University of Wisconsin-Madison, USA
[Regular] Scan data volume reduction using periodically alterable MUXs decompressor
Y. Han (Chinese Academy of Sciences, China), S. Swaminathan (IBM Micro Electronics, USA),
Y. Hu (Chinese Academy of Sciences, China), and A. Chandra (Synopsys Inc., USA)
[Regular] Efficient static compaction techniques for sequential circuits based on reverse order
restoration and test relaxation
A.H. El-Maleh, S.S. Khursheed, and S.M. Sait (King Fahd University of Petroleum and Minerals, Saudi Arabia)
[Regular] Low power test data compression technique for designs with multiple scan chains
Y. Shi (Waseda University, Japan), N. Togawa (The University of Kitakyushu, Japan), S. Kimura,
M. Yanagisawa, and T. Ohtsuki (Waseda University, Japan)
[Short] Threshold testing: covering bridging and other realistic faults
Z. Jiang and S. Gupta (University of Southern California, USA)
Session A9: Design for Testability: III
CHAIR: Hideo Fujiwara, Nara Institute of Science and Technology, Japan
[Regular] Synthesis of testable finite state machine through decomposition
B.K. Sikdar, A. Sarkar (Bengal Engineering and Science University, India), S. Roy (TTTI, Kolkata, India),
and D.K. Das (Jadavpur University, India)
[Regular] Shannon expansion based supply-gated logic for improved power and testability
S. Ghosh, S. Bhunia, and K. Roy (Purdue University, USA)
[Short] Flip-flop chaining architecture for power-efficient scan during test application
S. Gupta, T. Vaish (Indian Institute of Technology, Guwahati, India), and S. Chattopadhyay
(Indian Institute of Technology, Kharagpur, India)
[Short] A unified approach to partial scan design using genetic algorithm
V. Arora and I. Sengupta (Indian Institute of Technology, Kharagpur, India)
Session B9: Fault Modeling, Processor Testing, and Memory Testing
CHAIRS: Nicola Nicolici, McMaster University, Ontario, Canada
Arun Gunda, LSI Logic, USA
[Regular] A family of logical fault models for reversible circuits
I. Polian (Albert-Ludwigs University, Germany), J.P. Hayes (University of Michigan, USA), T. Fiehn,
and B. Becker (Albert-Ludwigs University, Germany)
[Regular] Compressing functional tests for microprocessors
K.J. Balakrishnan (NEC Labs,USA), N.A. Touba (University of Texas at Austin, USA), and S. Patil (Intel Corpn., USA)
[Regular] Investigations of faulty DRAM behavior using electrical simulation versus an analytical approach
Z.A-Ars (Delft University of Technology, The Netherlands), J. Vollrath and S. Hamdioui (Infineon Technologies AG, Germany)
[Short] Arithmetic test strategy for FFT processor
J-X. Xiao (Xihua University, China), G-J. Chen, and Y-L. Xie (University of Electronic Science and Technology, China)
[Short] Efficient constraint extraction for template-based processor self-test generation
K. Kambe (Nara Institute of Science and Technology, Japan), T. Iwagaki (Japan Advanced Institute of
Science and Technology, Japan), M. Inoue, and H. Fujiwara (Nara Institute of Science and Technology, Japan)
INDUSTRY SESSIONS
Session C1: SoC Test Practices
CHAIR: Shaleen Babu, Cadence Design Systems, India
IEEE Std 1500 compliant infrastructure for modular SoC testing
T. Waayers, E.J. Marinissen, and M. Lousberg (Philips Research Laboratories, The Netherlands)
DFT for low cost SoC test
R.A. Parekhji (Texas Instruments, Bangalore, India)
Managing test and repair of embedded memory subsystem in SoC
R. Chandramouli (Virage Logic, USA)
Session C2: Defect-Based Testing
CHAIR: T.M. Mak, Intel Corporation, India
The ultimate chase
P. Krishnamurthy (LSI Logic Corp., USA)
Defect-oriented test for ultra-low DPM
V. Iyengar and P. Nigh (IBM Microelectronics, USA)
Current testing for nanotechnologies: a demystifying application perspective
H. Manheave (Q-Star Test, Belgium)
Session C4: Advances in Test Generation and Verification
CHAIR: Jacob Abraham, University of Texas at Austin, USA
High level test generation for custom hardware: an industrial perspective
I. Ghosh (Fujitsu Laboratories of America, USA)
High level test generation / SW based embedded test
P. Parvathala (Intel Corporation, USA)
Verification of industrial design using a computing grid with more than 100 nodes
S. Iyer (University of Texas at Austin, USA), J. Jain (Fujitsu Laboratories of America, USA),
D. Sahoo (Stanford University, USA), T. Shimuzu (Fujitsu Laboratories of America, USA)
Session C5: Test Data Compression and System Level Testing
CHAIR: Sudhakar M. Reddy, University of Iowa, USA
Emerging techniques for test data compression
K. Balakrishnan (NEC Laboratories America, USA)
Improving test quality using test data compression
N. Mukerjee (Mentor Graphics Corporation, USA)
Efficient test architecture based on boundary scan for comprehensive system test
T.J. Chakraborty (Lucent Technologies, USA)
Session C6: Mixed Signal Testing
CHAIR: Rajib Mantri, Texas Instruments, India
Challenges in next generation mixed-signal IC production testing
S. Cherubal (Wiquest Communications, USA)
Practices in testing of analog mixed-signal and RF SoCs
S. Abdennadher (Intel Corporation, USA) and S.A. Shaikh (Sun Microsystems, USA)
Challenges in high speed interface testing
S. Abdennadher (Intel Corporation, USA) and S.A. Shaikh (Sun Microsystems, USA)
Session C7: Delay Testing and Burn-in Test Methodologies
CHAIR: Zainalabedin Navabi, University of Tehran, Iran
Practical aspects of delay testing for nanometer chips
V. Chickermane, B. Keller, K. McCauley, and A. Uzzaman (Cadence Design Systems, USA)
Limitation of structural scan delay test
T.M. Mak (Intel Corporation, USA)
Shortening burn-in test: application of a novel approach in optimizing burn-in timing using
Weibull statistical analysis with HVST
F. Zakaria (Freescale Semiconductor, Malayasia), M.PL. Ooi (Monash University, Malayasia),
Z.A. Kassim (Freecale Semiconductor, Malayasia), and S. Demidenko (Monash University, Malayasia)
-----------------------------------------------------------------------------------------------------------------------------------------------
------------------------------
![[BACK]](../../images/icon-square-left-s.gif)
RETURN